1. Field of the Invention
The present invention relates generally to an apparatus and a method for satellite Digital Multimedia Broadcast (DMB), and more particularly to an apparatus and a method for convolutional interleaving and deinterleaving in a satellite DMB system.
2. Description of the Related Art
Generally, viterbi decoders or Reed-Solomon (RS) decoders, which are used for a digital signal transmission, have superior error correction abilities. However, it is difficult for the decoders to correct continuously occurring burst errors that are larger than a predetermined size. In order to complement the aforementioned disadvantage, a sequence of input signals is changed by an interleaver/deinterleaver, such that the burst errors are dispersed. Therefore, the decoders may efficiently perform error correction.
FIG. 1A is a block diagram illustrating a conventional digital transmitter and receiver using an interleaver and a deinterleaver, and FIG. 1B is a diagram illustrating a change of signals interleaved by an interleaver.
Referring to FIG. 1A, an encoder 101 of the transmitter adds supplementary information to a signal or changes types of a signal for an error correction in the receiver. Reference number 105 of FIG. 1B represents a signal encoded by the encoder 101. The signal 105 will be changed by the interleaver 102. Reference number 106 of FIG. 1B represents the signal 105 having the sequence changed by the interleaver 102. The signal 106 having passed through the interleaver 102 includes three continuous errors occurring in portions A1, A14, and A11 due to exterior errors or noise, as shown in a reference number 107. If the number of burst errors capable of being corrected by an encoder 101 and a decoder 104 is two, it is impossible to properly correct the three continuous errors. However, an order of the signal 106 that is passed through the interleaver 102 reverts to an original order of the signal in a deinterleaver 103 in the receiver, such that the burst errors are dispersed. Accordingly the decoder 104 can properly correct the errors.
Additionally, the interleaver and deinterleaver described above may be generally classified into a block interleaver and a convolutional interleaver.
FIG. 2 illustrates a conventional convolutional interleaver and deinterleaver having superior characteristics in memory efficiency. Referring to FIG. 2, a first input signal is input to a 0th row 201 of the interleaver and the next input signal is input to a 1th row 202. Accordingly, after a signal is input to a final (n−1)th row 203, a signal is input to the 0th row 201 again. Because each row has different buffer sizes, input signals are differently delayed. Therefore, an output sequence is different from the input sequence. That is, a buffer delay does not exist in the 0th row 201 and a buffer delay of ‘1×m (m has a predetermined value)’ exists in the 1st row 202.
Accordingly, the deinterleaver is required in to enable the output sequence to coincide with the input sequence. In the deinterleaver, buffers are arranged along the rows in an order based on the buffer sizes, which is opposite to the order of the buffers arranged in the interleaver, so that the final output signal coincides with the input signal of the interleaver.
FIG. 3 is a block diagram illustrating the interleaver illustrated in FIG. 2. Referring to FIG. 3, a row counter 300, which represents a row location of the interleaver, counts an input signal each time the input signal exist and obtains row information corresponding to a current input value. A column counter 301 counts a value of the row counter 300, which corresponds to the column counter 301, each time the value of the row counter generates and indicates a buffer location of the interleaver.
An address generator 303 generates an address of an outer memory 305 corresponding to a current input signal using different counter information, that is, information from the row counter 300 and the column counter 301. If the address is generated, a control signal generator 304 generates a read command, reads a memory value written before the address from the outer memory 305, and outputs the read memory value. The control signal generator 304 generates a write command and writes a new input signal in a location of an address equal to the address so that an interleaving operation is ended.
However, it is possible to make a wider range of change in the sequence, only when the number of rows in the interleaver and deinterleaver, and a deviation between buffer sizes of the rows increase according to a burst error increase, thereby dispersing the continuous errors. In such a case, because the size of a memory used as a delay buffer increases, the outer memory illustrated in FIG. 3 is used. When there is no outer memory corresponding to magnitudes of signals input and output to and from the interleaver, an interface between the interleaver and the outer memory is complicated.
Further, when there is no memory corresponding to magnitudes of signals input and output to and from the interleaver, all input signals pass through an interleaving process. Accordingly, when the address generator generates an address corresponding to the input signal and performs a reading operation and a writing operation for the outer memory, an access frequency between the interleaver and the outer memory increases. Consequently, power consumption increases.
Further, as illustrated in FIG. 2, it is simple to construct the convolutional interleaver and deinterleaver using a First Input First Output (FIFO). However, the convolutional interleaver is actually constructed using the block-type memory as illustrated in FIG. 3. Accordingly, the convolutional interleaver and deinterleaver must generate an address value of the memory using row information, which is a row value of the interleaver and deinterleaver to be read and written for current information, and location information of a buffer of a corresponding row. Therefore, when the address value of the memory increases, the number and the magnitudes of the counters also increase. Consequently, the number of the gates increases.
The conventional interleaver and deinterleaver have a complex construction because they use complex equations to generate the address of the outer memory and include counters using many registers. Further, in interfacing with the outer memory, the interleaver and deinterleaver transfers simple input signals or sequentially bundled input signals, such that power consumption increases.